In recent years, apparatuses having picture output functions, e.g., smartphones, tablet computers, television receivers, and game machines, have had remarkable improvement in display resolution. For adaptation thereto, there has been expansion of a memory band desired for an image processor LSI (Large Scale Integrated Circuit) installed in such apparatuses. Known techniques to achieve a wide memory band may include Chip on Chip (CoC), as disclosed in Patent Literature 1. But the CoC technique may tend to incur higher costs, because of use of DRAM (Dynamic Random Access Memory) having a special interface, or use of techniques such as fine connection using microbumps. A general approach may be, therefore, to use a plurality of DRAMs having a standard DDR (Double Data Rate) interface and to ensure the memory band by increasing the number of connection channels between the image processor LSI and the DRAMs. A 64-bit interface is in actual use in apparatuses such as smartphones, and the use of such an interface is expected to be spreading in the future.
Moreover, miniaturization of semiconductor devices has allowed for integration of a greater number of transistors in a chip. This has made it possible to integrate even more functions in one chip. For example, an application processor currently used in the smartphone or the tablet computer, and the LSI incorporated in a digital television receiver mainly use what unitizes CPU (Central Processing Unit), GPU (Graphics Processing Unit), and various interfaces as one chip.
Such advances in multi-channeling of a memory interface and in functional integration in one chip have caused a tendency of an increase in the number of terminals that connect the LSI to outside. In related arts, a packaging method has been generally adopted in which a semiconductor chip is connected to a packaging substrate by wire bonding. In recent years, however, in order to adapt to the increase in the connection terminals, adoption of a so-called flip chip technique has been increasing. The flip chip technique involves connecting the semiconductor chip to the packaging substrate with use of solder bumps. In particular, a technique generally used in the flip chip technique is called C4 (Controlled Collapse Chip Connection), as disclosed in, for example, Patent Literature 2.
In the C4 technique, on side of the packaging substrate, a solder resist may be provided in advance with apertures. The apertures each may have a substantially same size as a size of a solder bump to be used for connection. A paste solder material may be printed in the apertures. Then, a chip provided in advance with solder bumps may be mounted on the printed solder material, with use of flux. By a batch reflow method, the solder may melt to form connection. An underfill resin may be filled for sealing, between the chip and the packaging substrate. With this technique used, miniaturization of an inter-terminal pitch may become difficult, for the following reasons. First, in order to ensure a gap between the chip and the packaging substrate to fill the underfill resin, it is desirable to increase a diameter of the solder bump formed on side of the chip. Second, the solder paste may be formed by a printing method, causing difficulty in formation of fine patterns. Accordingly, the pitch between the connection terminals may become about 150 μm to 180 μm both inclusive. This leads to expectation of difficulty in adaptation to an increase in the number of signals in the future, or to chip shrinkage due to device miniaturization.
In view of the current situation as described above, Patent Literature 3 discloses a technique that involves performing flip chip directly on wirings, for purpose of a further increase in signal terminal density and reduction in substrate costs. In the existing C4 technique, a land having a larger size than the bump diameter may be formed on the packaging substrate. In contrast, in this technique, a bump may be pressed onto a wiring having a smaller width than a bump diameter, to join the bump and the wiring together, with the wiring forcing itself into the bump. Thus, this technique has made improvement in an effort to attain high bonding strength even in a case with use of bumps having small diameters. Also, a bump structure may be generally used in which solder plating is performed on a metal pillar, or a so-called pillar. This makes it possible to ensure the gap, between the chip and the packaging substrate, desirable for injection of the underfill resin even in the case with use of bumps having small diameters.
A shortened pitch between the bumps may naturally result in possibility of occurrence of a short circuit between wirings. Patent Literature 4 therefore proposes to selectively cover a spot that is concerned about the occurrence of the short circuit with a masking material such as a solder resist. But this structure may cause the following disadvantages. First, the partially-formed masking material may easily peel off because of lack of continuity with other masking materials formed on the packaging substrate. When the partially-formed masking material peels off during an assembly process, there may be expectation of hindrance to injection of the underfill resin, or failure to prevent the short circuit. Second, the wirings are exposed in other than the spot where the masking material is partially formed. This causes possibility of the occurrence of the short circuit due to the solder material. Moreover, in a case with low adhesion between the underfill resin and the packaging substrate, a cavity may be formed between the wirings. In a case of moisture absorption, there may be concern about occurrence of migration. Third, because the masking material has an aperture in wide ranges, the wirings may easily peel off from an insulating layer of the packaging substrate, due to stress during the assembly process or after shipment of a product. This may cause lowered operation reliability.
To cope with the disadvantages described above, Patent Literature 5 proposes a technique to selectively provide the masking material (solder resist) with an aperture at a connecting part between the wiring and the bump. Such a structure allows for lower probability of the occurrence of the short circuit between the adjacent wirings.